1. Field of the Invention
The present invention relates to the field of solid state electronics and more particularly to the field of solid state electronic logic circuits.
2. Description of the Prior Art
In designing logic circuits, attempts have been made to obtain the benefits of Gallium Arsenide (GaAs) technology while minimizing the disadvantages. In particular, GaAs provides considerably greater field effect transistor (FET) channel electron mobility than conventional semiconductors. Further, GaAs wafers exhibit very low parasitic capacitance. These factors allow fabrication of much faster transistors in GaAs than silicon.
Since GaAs depletion-mode metal-semi conductor FET (MESFET) technology has the longest manufacturing history of the GaAs technologies, the depletion-mode technology presently offers more promise for easy, cost-effective production of commercial GaAs logic circuits. In GaAs logic circuit applications, MESFET threshold voltages may range from +0.4 to -2.0 V and gate-source voltages may be as low as -3.0 V. As the gate-source supply voltage becomes more negative, power dissipation increases. As threshold voltages approach 0.0 V, less negative (lower power) gate-source supply voltages can be used, reducing power dissipation. Reduced power dissipation becomes important in designing GaAs logic gate arrays of appreciable size (eg. larger than 80 gates). In depletion-mode GaAs FET logic gate array designs, where power dissipation may be several milliwatts per gate, the ability to use low power supply voltages is very important. However, since manufacturing tolerances become critical as threshold voltages approach 0.0 V, a common compromise for the nominal low voltage supply is -2 V. While this eases manufacturing tolerances, which are of critical concern to cost-effective commercial manufacture of logic gate arrays, the low nominal power supply voltage limits the nominal voltage swing of the output of the circuit. Although this reduced nominal output voltage swing increases the switching speed of the output of the circuit, it substantially reduces the noise margin of the next logic circuit. As a result, the reduced nominal output voltage swing increases the susceptibility of the next logic circuit to triggering in response to unwanted noise in the connecting lines.
Although depletion-mode FET manufacturing technology has the longest manufacturing history of the GaAs technologies, depletion-mode FETs made from present day GaAs technology still have relatively poor matching qualities, which increases the difficulty of designing cost-effective logic gate arrays using large numbers of gates. Device matching problems and process limitations are even greater problems in enhancement-mode FET circuit production. In particular, due to limitations in the production of both of these technologies, from device to device on a single logic gate array chip, the logic threshold voltage and output voltage may vary considerably. In a gate array, this is a substantial problem since any one input gate of a given logic circuit can be connected to an output gate of any other logic circuit. These variations in input logic threshold voltage and output voltage can decrease noise margins and interfere with the intended system operation.
Even when such depletion-mode and enhancement-mode circuits are designed to be insensitive to such variations in input logic threshold voltages and output voltage swing, under certain operating conditions the output voltage swing will be reduced due to forward biasing of an FET. In particular, the source resistance inherent in the FET produces an undesired voltage drop in response to increased gate current resulting from forward biasing of the FET. This adds to the drain-to-source voltage drop across the FET, which reduces the output voltage swing when the FET is used in an inverter. Also, as the operating temperature of the circuit increases, the voltage drop across circuit diodes decreases. This applies both to diodes connected to the FET and to the gate-source junction diode of an inverter FET and results in increased gate current. The increased gate current adds to the above-described reduction of output voltage swing due to an increase in the source resistance of the FET as the operating temperature increases.
Prior FET logic circuits have coupled FETs with parallel connected Schottky diodes used in an input stage (FIG. 1). When the FETs include an inverter FET in series with a pull up FET, with the output node between the FETs, the output voltage swing is limited by the voltage of a power supply connected to the inverter FET. This output voltage swing occurs under no loud or load conditions. When several such Schottky diodes are used in the input stage in series with a pull down FET to apply gate voltage to the inverter FET, the output voltage swing is substantially reduced since each Schottky diode in the input stage acts as an active pull down through the pull down FET. In such an SDFL circuit, any fan out requirements in excess of two or three input circuits can severely reduce noise margin due to reduced output voltage swing, increased output capacitance and current loading problems. This can result in the circuit itself reducing yield when used in a large scale logic gate array. Further, the input capacitance to such an SDFL circuit is relatively large due to the lack of isolation between the input stage and the gate of the inverter FET which exhibits Miller multiplication of its drain-to-gate capacitance.
Finally, the pull up FET and the output FET are sized large to provide the high output current needed to maintain fast switching speed of capacitive output loads. The large pull up FET size results in supplying high current to the next input stage.
In prior buffered FET logic (BFL), an input stage includes an inverter FET for each of the logic inputs (FIG. 2). The inverter FETs are connected in parallel across a power supply and a pair of output FETs. One of the pair of FETs is connected as an active load and one is connected as an output source-follower to ensure output signal compatibility with later logic stages. Such BFL is not limited by fan out problems as in SDFL because the inverter FETs form high impedance, low input current input stages that are coupled directly to the logic output without significant degradation of the input voltage levels, the input impedance, or the waveform rise time. However, if the input stages are connected to a -1 V power supply and an output FET is connected to a -2 V power supply for compatibility with voltages used with ECL circuits, the output voltage swing will be less than -1 V, rendering the noise margin poor and the BFL circuit thus very susceptible to noise pulses that can induce error signals into a large gate array. These error signals are caused, for example, by poor device matching and temperature variations that result in comparable input logic circuit FETs that have the same nominal threshold voltage actually having different threshold voltages. These variations also result in deviations from nominal in the output voltage swing. Such error signals are also caused by noise or voltage gradients due to IR drops.
On the other hand, if the output voltage swing to the input devices were increased (for increased noise margin) by changing the input stage power supply to -2 V and the output FET power supply to -5.2 V, there is a greater risk that the input would draw current due to forward biasing of the gatesource junction of the output FETs, which would limit the output voltage swing. Further, this would result in higher power consumption.
Also, where the output source-follower FET drives a Schottky diode connected to the output FET, more power is dissipated by the diode when a high capacitance load is connected to the output. The increased power dissipation results from the increased current that is required to maintain the switching speed of the circuit.
Known prior BFL and SDFL circuits have not limited the current to the gate of the output FET and have thus not overcome the problems which are overcome by the circuits of the present invention.